# alexforencich/verilog-ethernet — RepoVerse

Verilog Ethernet components for FPGA implementation

URL: https://repoverse.app/cards/26883874

[Repository source](https://github.com/alexforencich/verilog-ethernet)

## Card snapshot

- Edition: Genesis
- Rarity: common
- Finish: Base
- Attack: 3094
- Defense: 6122
- GitHub stars: 3135
- GitHub forks: 862
- Language: Verilog
- Category: Open Source Classics
- Snapshot date: 2026-10-22

These repository statistics and game attributes belong to this dated card snapshot. They are not a current assessment of software quality.

This page describes the repository card, without a holder or individual copy record.

- [Rules](https://repoverse.app/rules.md)
- [Explore](https://repoverse.app/explore)